1Features
- 40 analog outputs: 16 × 0–12 V gain control, 16 × 0–12 V band control, 8 × ±5 V AGC
- Three 16-channel, 12-bit DACs, each reached by the FPGA over its own LVDS SPI link
- Precision output stages on 0.1 % resistors, stable into cable capacitance
- The ±5 V zero point follows the DAC reference, so reference drift can't shift it
- Every channel on its own MCX connector, with ESD protection
- 12 V input with surge, reverse-polarity and EMI protection; isolated ±15 V for the outputs
2Specifications
- Channels
- 40
- Outputs
- 32 × 0–12 V · 8 × ±5 V
- Resolution
- 12-bit
- Host link
- SPI over LVDS
- Host
- UltraScale FPGA
- Connectors
- MCX, one per channel
- Input
- 12 V
- Component count
- 540+
- Schematic
- 6 sheets
- Design tool
- Altium Designer
3Figure 1 — Schematic
Restricted
Images for this project are shared on request.
4Description
A module in a VPX system that turns digital settings from an UltraScale FPGA into forty analog control voltages: sixteen for gain, sixteen for band selection and eight for AGC. Each group comes from one 16-channel, 12-bit DAC, and the FPGA reaches each DAC over SPI carried on LVDS pairs, so the control lines stay differential until they arrive at the converter.
The DACs' 0–2.5 V outputs are scaled in precision op-amp stages. The gain and band banks are amplified to 0–12 V; the AGC bank is scaled and shifted to ±5 V against an offset derived from the DAC's own reference, so mid-scale stays at 0 V however the reference drifts. Each output drives its connector through a series resistor inside the feedback loop, which keeps the stage stable into cable capacitance, and every bank can run its op-amps from a negative rail or from ground.
Power arrives as 12 V through a TVS, a resettable fuse, a reverse-polarity MOSFET and a common-mode filter. A 5 V buck runs in forced-PWM at a fixed 1 MHz to keep its ripple low and predictable, feeding separate analog and digital 3.3 V LDOs, and an isolated converter makes the ±15 V the output stages need.
5Schematics
Restricted
6 schematic sheets and a block diagram — unlocked with the password in Figure 1.