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Enes Cavus
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FPGA06 / 15

FPGA Encoder IP

Vivado IP block for reading SSI-interface encoders.

1Features

  • Packaged as a reusable Vivado IP block
  • Reads absolute encoders over the SSI interface
  • Written in VHDL

2Specifications

Interface
SSI
Language
VHDL
Toolchain
Vivado

3Figure 1 — Board

FPGA Encoder IP

4Description

This part is documented as preliminary — the full characterisation is not written up yet. For schematics, constraints, or what went wrong and how it got fixed, ask directly.

5Design tools

VivadoVHDL